Typically, in electronic systems, a processor or processing logic may retrieve data or a data structure from system memory over a high-speed and consequently high-power input/output (“I/O”) interface. After processing, the data may be output over a slower and lower power I/O interface. To reduce power dissipation, these systems typically employ buffers, such as first-in, first-out (“FIFO”) buffers. The buffers stage the data while it is consumed by the processor and output over the slower I/O interface. The buffers facilitate power conservation by allowing the high-power I/O interface to quickly output a portion of the data or data structure from system memory and power down until another portion of data is required.
The amount of time that the high-power I/O interface is powered down, thereby dissipating less power, may be related to various characteristics of the system, for example, the size of the buffer. Increasing the size of the buffer in order to power down the high-speed I/O interface for longer periods of time, however, has typically been avoided. As the size of the memory buffer increases, there is a similar increase in leakage power. This may result from the entire memory buffer receiving a single operational power level. Those memory banks which are not in use (e.g. not being accessed) dissipate an equivalent amount of power compared to the memory banks which are currently in use. Consequently, any power savings achieved by powering down the I/O interface for longer periods of time are typically offset by the additional leakage power dissipated by the increased size of the memory buffer.